The present invention relates to a method of manufacturing a semiconductor device using the ion implantation technique.
In manufacturing a semiconductor device, the ion implantation technique is generally employed, in which a photoresist is formed as a mask for selectively implanting ions into a substrate which is a target of implantation.
A photoresist functions as a mask in either case of selectively forming an insulating film and a conductive film on a substrate or selectively performing thermal diffusion of impurities on a surface of the substrate. Needless to say, a photoresist functions as a mask also when selectively performing ion implantation of impurities into a surface of the substrate.
When a photoresist is used as a mask for ion implantation, problems arise as will be described below.
The first problem is that the photoresist is difficult to be removed particularly when performing ion implantation of impurities of high concentration. Ion implantation causes ions to enter into the photoresist serving as a mask. The photoresist hardens accordingly, and may become difficult to be removed. As a result, resist residues may be generated, causing a reduction in yields of products.
To remove the photoresist without leaving residues, plasma ashing may be intensified or wet etching may be carried out rather excessively. However, intensification of ashing may inflict considerable charging damage upon the substrate, resulting in a reduction in the reliability of products. On the other hand, excessive wet etching and ultrasonic cleaning may cause a minute circuit pattern such as a gate electrode to fall or to be removed. Thus, it is not desirable to intensify ashing or carry out excessive wet etching.
In other words, there has been a problem of reducing the area in which a photoresist hardens in order to remove the photoresist easily, thereby improving its removability.
The second problem relates to the dimensional accuracy of the photoresist. The more minute the circuit pattern, the stricter the requirement for the dimensional accuracy of the photoresist needed for an implantation process.
For instance, when performing ion implantation into source/drain regions of a metal oxide semiconductor (MOS) transistor, a conventional photoresist has been provided with openings sufficiently larger than source/drain regions since a large element isolating layer is formed around the source/drain regions. However, as a pattern of elements and circuits becomes more minute, a different element may be provided immediately next to the MOS transistor, and it should be ensured that ions for forming the source/drain regions should not be implanted into the different element. Thus, the dimensional accuracy of the openings needs to be improved.
When the density of the openings in the photoresist vary with the location, however, the shape of the openings are easily changed. This will be described below referring to FIGS. 22 and 23.
FIG. 22 illustrates a wafer WF with product chips such as CP1 to CP4 formed on its surface. FIG. 23 is a magnified view of a boundary region R among the product chips CP1 to CP4. FIG. 23 illustrates a space area AR1 with no element or circuit formed therein provided in the product chip CP1 at the right of the region in which N-channel MOS transistors N1 and N2 and P-channel MOS transistors P1 and P2 are formed. The product chips CP2 to CP4 are similarly provided with space areas AR2 to AR4 having no element or circuit formed therein, respectively.
Openings of the photoresist cannot not be provided in such space area AR1 having no element or circuit formed therein. In other words, the density of the openings in the photoresist is high in the region in which the N-channel MOS transistor N1 and the like are formed, whereas the density is low in the space area AR1.
Generally, a photoresist tends to have a higher surface tension as it occupies a larger area. Thus, when the space area AR1 having no element or circuit formed therein is large, the photoresist in the region in which the N-channel MOS transistor N1 and the like are formed is pulled by the photoresist present on the side of the space area AR1. As a result, the openings provided for forming elements are deformed in shape toward the space area AR1, which tends to cause degradation in the dimensional accuracy of the openings.
An effective method of improving the dimensional accuracy of the photoresist is to make it thin in film thickness. The photoresist, when having a great film thickness, is strongly pulled by the surface toward the space area AR1 to increase the amount of deformation of the shape of the openings, whereas making the film thickness thin can achieve a reduction in the amount of deformation.
On the contrary, with such thin film, the photoresist might not function sufficiently as a mask in ion implantation. This is because ions penetrate through the thin photoresist to be implanted to the outside of a desired region.
In short, there has been a problem of improving the dimensional accuracy of a photoresist without making it thin in film thickness.
Referring now to the third problem, when a neutralizer that neutralizes charges of ions rushing into a substrate is degraded in performance, the ions are trapped in the photoresist to cause charge-up, resulting in electrostatic discharge damage in a gate insulating film and a capacitor dielectric film provided in the vicinity of the photoresist.
With electrostatic discharge damage caused in the gate insulating film and the capacitor dielectric film, a normal operation cannot be performed with a poor breakdown voltage, resulting in generation of a fail chip. Even if electrostatic discharge damage is not caused, damage might remain partly in the gate insulating film and the capacitor dielectric film. Such damage, although caused partly, generates a leakage current even if an operation is performed, which also results in generation of a fail chip.
In other words, there has been a problem of preventing the occurrence of charge-up of a photoresist.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the resist removability by reducing the area in which a photoresist hardens in ion implantation and the dimensional accuracy of the photoresist as well as preventing the occurrence of charge-up of the photoresist.
An aspect of the invention is directed to a method of manufacturing a semiconductor device. The method includes the following steps of (a) to (c). The step (a) is forming a photoresist on a semiconductor substrate. The step (b) is performing patterning of the photoresist. The step (c) is performing ion implantation into the semiconductor substrate using the photoresist as a mask. In the patterning performed in the step (b), an opening is provided as a dummy pattern as well as an opening as a pattern of elements and circuits in a space area other than the pattern of elements and circuits in one chip.
With the method of the aspect, the photoresist for ion implantation is provided with the opening as the dummy pattern. Thus, the area of region other than the opening in the photoresist is reduced, which can reduce the number of ions entering into the photoresist. As a result, the resist removability can be improved by reducing the area in which a photoresist hardens. Further, the possibility of charge-up can be reduced by reducing the number of ions entering into the photoresist. Furthermore, with a reduction in the area of region other than the opening in the photoresist, there can hardly be present a location where strong surface tension is generated. Consequently, this allows the dimensional accuracy of the photoresist to be improved without making the photoresist thin in film thickness.
Preferably, in the method, a conductive material in contact with an end of the dummy pattern is formed on a surface of the semiconductor substrate exposed to the opening as the dummy pattern.
With the method, the conductive material in contact with the end of the dummy pattern is formed on the surface of the semiconductor substrate exposed to the opening as the dummy pattern. Thus, ions entered into the photoresist in ion implantation become easy to escape into the semiconductor substrate through the conductive material. Consequently, a further improvement in removability of the photoresist and a further reduction in the possibility of charge-up can be achieved.
Preferably, in the method, an active region in contact with an end of the dummy pattern is formed in a surface of the semiconductor substrate exposed to the opening as the dummy pattern.
With the method, the active region in contact with the end of the dummy pattern is formed on the surface of the semiconductor substrate exposed to the opening as the dummy pattern. Thus, ions entered into the photoresist in ion implantation become easy to escape into the semiconductor substrate through the active region. Consequently, a further improvement in removability of the photoresist and a further reduction in the possibility of charge-up can be achieved.
Preferably, in the method, a dicing line is formed in a surface of the semiconductor substrate, and the opening as the dummy pattern is provided on or close to the dicing line.
With the method, the opening as the dummy pattern is provided on or close to the dicing line. The photoresist can thus be separated chip by chip, which can prevent the difficulty in removing the photoresist and the possibility of charge-up per chip. As a result, this can prevent the effect of degradation, if any, caused in a chip from being exerted on another chip. When the opening as the dummy pattern is provided on the dicing line, ions entered into the photoresist in ion implantation become easy to escape into the semiconductor substrate through the dicing line, resulting in a further improvement in removability of the photoresist and a further reduction in the possibility of charge-up.
Preferably, in the method, the ratio of the area of the opening as the dummy pattern to the whole area of one chip is adjusted in accordance with the area of the opening as the pattern of elements and circuits.
With the method, the ratio of the area of the opening as the dummy pattern to the whole area of one chip is adjusted in accordance with the area of the opening as the pattern of elements and circuits. Such adjustment of the area of the opening in the photoresist permits optimization of the effects of improving the removability of the photoresist, improving the dimensional accuracy and preventing the occurrence of charge-up.